Minimalistic resets coding style

I wanted to write a post about resetting signals of complex types, but I decided that I have to write two other ones to make sure that we are on the same page.

There is a nice document called Get Smart About Reset: Think Local, Not Global. If you haven't read it yet - do it. One of its points - eliminate as much unnecessary resets as you can.
My experience says me that resets cause big problems in big high speed designs, and I always try to reduce number of resettable registers.
But there is a trap. Let's consider this code (VHDL, but for Verilog all this works the same way):

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process(clk) is begin if rising_edge(clk) begin if rst = '1' then a <= '0'; else a <= somecode; b <= someothercode; end if; end if; end process;

As you can see I don't reset "b", but in fact it won't work as intended. If rst='1' then "b" must retain it's value and instead of getting rid of rst signal coming to reset pin of "b" FF we get the same signal coming to CE pin of the same FF. It's clearly won't help reducing reset signal's fanout.
What I actually do is this:

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process(clk) is begin if rising_edge(clk) begin a <= somecode; b <= someothercode; if rst = '1' then a <= '0'; end if; end if; end process;

You can see that "b" don't care about reset at all now. Synthesis tool creates exactly what we wanted. (at least Vivado does).
As you can see it is also reads easily and looks good. I always use this style, except for testbenches, as it doesn't always works with variables.
Leave a comment if you have any thoughts about this.