Minimalistic resets coding style

I wanted to write a post about resetting signals of complex types, but I decided that I have to write two other ones to make sure that we are on the same page.

There is a nice document called Get Smart About Reset: Think Local, Not Global. If you haven't read it yet - do it. One of its points - eliminate as much unnecessary resets as you can.
My experience says me that resets cause big problems in big high speed designs, and I always try to reduce number of resettable registers.
But there is a trap. Let's consider this code (VHDL, but for Verilog all this works the same way):

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process(clk) is begin if rising_edge(clk) begin if rst = '1' then a <= '0'; else a <= somecode; b <= someothercode; end if; end if; end process;

Unsafe FPGA/ASIC neighbors

Do you remember Spectre/Meltdown? Unsafe code on your processor can indirectly access data in memory locations which should have been isolated from the code.
Similar things can happen in FPGA/ASIC world. It can be that your sensitive data (e.g. ciphering keys) are used in your IP and there is another (rogue) IP on the same device. For example, you bought an IP from a malicious vendor, or you are sharing a big FPGA with an attacker on some cloud infrastructure.
Despite that your IPs are logically separated, they share the power distribution network of the device and variation in power consumption of your core, correlated with your sensitive data can be sensed by the other core using signal propagation speed/voltage dependency.

More details in the article
An Inside Job: Remote Power Analysis Attacks on FPGAs
Falk Schellenberg, Dennis R.E. Gnad, Amir Moradi, and Mehdi B. Tahoori