Simple and efficient FPGA reset method (reset for records)

I hope you are using VHDL records extensively. They are not as powerful as SystemVerilog data types and interfaces, but it's a huge step forward from individual bits and bit arrays of Verilog. I don't understand why some people use VHDL and don't use this feature of VHDL! Records make your code significantly clearer and crisper. They reduce risk of forgetting to assign a value to a signal of a complex data bus and make your description 10 times shorter while improving readability.