I wanted to write a post about resetting signals of complex types, but I decided that I have to write two other ones to make sure that we are on the same page.
There is a nice document called Get Smart About Reset: Think Local, Not Global. If you haven't read it yet - do it. One of its points - eliminate as much unnecessary resets as you can.
My experience says me that resets cause big problems in big high speed designs, and I always try to reduce number of resettable registers.
But there is a trap. Let's consider this code (VHDL, but for Verilog all this works the same way):
1 2 3 4 5 6 7 8 9 10 11 | process(clk) is begin if rising_edge(clk) begin if rst = '1' then a <= '0'; else a <= somecode; b <= someothercode; end if; end if; end process; |