Simple and efficient FPGA reset method (reset for records)

I hope you are using VHDL records extensively. They are not as powerful as SystemVerilog data types and interfaces, but it's a huge step forward from individual bits and bit arrays of Verilog. I don't understand why some people use VHDL and don't use this feature of VHDL! Records make your code significantly clearer and crisper. They reduce risk of forgetting to assign a value to a signal of a complex data bus and make your description 10 times shorter while improving readability.

Minimalistic resets coding style

I wanted to write a post about resetting signals of complex types, but I decided that I have to write two other ones to make sure that we are on the same page.

There is a nice document called Get Smart About Reset: Think Local, Not Global. If you haven't read it yet - do it. One of its points - eliminate as much unnecessary resets as you can.
My experience says me that resets cause big problems in big high speed designs, and I always try to reduce number of resettable registers.
But there is a trap. Let's consider this code (VHDL, but for Verilog all this works the same way):

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process(clk) is begin if rising_edge(clk) begin if rst = '1' then a <= '0'; else a <= somecode; b <= someothercode; end if; end if; end process;

Unsafe FPGA/ASIC neighbors

Do you remember Spectre/Meltdown? Unsafe code on your processor can indirectly access data in memory locations which should have been isolated from the code.
Similar things can happen in FPGA/ASIC world. It can be that your sensitive data (e.g. ciphering keys) are used in your IP and there is another (rogue) IP on the same device. For example, you bought an IP from a malicious vendor, or you are sharing a big FPGA with an attacker on some cloud infrastructure.
Despite that your IPs are logically separated, they share the power distribution network of the device and variation in power consumption of your core, correlated with your sensitive data can be sensed by the other core using signal propagation speed/voltage dependency.

More details in the article
An Inside Job: Remote Power Analysis Attacks on FPGAs
Falk Schellenberg, Dennis R.E. Gnad, Amir Moradi, and Mehdi B. Tahoori

Features of for... loop in VHDL

If you didn't noticed, in my previous post I used "for" like "foreach" across enumerate type

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type LaneIndex is (L0,L1,L2,L3); ... for Lane in LaneIndex loop

In fact, you also can use it like that

for i in Arr'range loop

if Arr is an array.

Or you can use it like that:

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subtype LanesRange is integer range 0 to LanesInCore-1; ... for Lane in LanesRange loop

Highly recommend!

Special index types of VHDL arrays

Actually, in VHDL your array don't have to have integer indexes.

1 2	type ByteIndex is (B0,B1,B2,B3); type LaneType is array (ByteIndex) of std_logic_vector(7 downto 0);

I used this fact when I had to use multidimensional arrays to prevent mistakes when you mix up dimensions of your arrays.
For example, let's suppose you have a bus, consisting of 4 lanes and each of the lanes contains 4 bytes.

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type LaneType is array (0 to 3) of std_logic_vector(7 downto 0); type LaneBusType is array(0 to 3) of LaneType; ..... for Lane in 0 to 3 loop L(Lane)(0)(i) <= not L(Lane)(0)(i); --OK -- L(0)(Lane)(i) <= not L(0)(Lane)(i); -- error, but absolutely legal end loop;

In contrast, if you use non-integer indexes:

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type LaneIndex is (L0,L1,L2,L3); type ByteIndex is (B0,B1,B2,B3); type LaneType is array(ByteIndex) of std_logic_vector(7 downto 0); type LaneBusType is array(LaneIndex) of LaneType; signal clk : std_logic; signal L : LaneBusType := (others => (others => (others => '0'))); begin process is begin clk <= '0'; wait for 5 ns; clk <= '1'; wait for 5 ns; end process; process(clk) is variable i : natural := 0; begin if rising_edge(clk) then for Lane in LaneIndex loop L(Lane)(B0)(i) <= not L(Lane)(B0)(i); --OK -- L(B0)(Lane)(i) <= not L(B0)(Lane)(i); -- type error near b0 ; current type byteindex; -- expected type laneindex end loop; i := (i+1) mod 8; end if; end process;

The method helps you to avoid mistakes by controlling types of indexes. On the other hand, it adds some hassle. It is up to you when to use it.

How to save your plants, while you are away from your home

There is a simple and efficient trick to save your plants while you cannot water them. The trick uses Capillary action.

All you need is an old towel (or another peace of cloth) and a big bowl. You place your plants around the bowl with water, cut your cloth on ribbons and dip one ends of each ribbon to the bowl and cover soil in your pots with the other ends of the ribbons.

Ends of the ribbons should reach the bottom of the bowl and there must be plenty of water in it, as plants consume it a lot! What you see on the photo is what left after a week of absence during cold, cloudy weather. There was more than a half of the bowl of water a week ago.

Pebbles and shells in the middle of the bowl are just for aesthetics reasons and have no purpose.

I must tell you that each time when I am back the plants look much healthier then before I left them. I am even thinking about installing of a some sort of drip irrigation system for them.

Of course, you can just use one of this self watering planters, but I think it is cheating. :)